The present invention relates to a signal processing circuit and a semiconductor device including the signal processing circuit, for example, a semiconductor device including a chopper amplifier.
It is difficult for an amplifier or a comparator to secure accuracies of amplification of an input signal and comparison because of an offset voltage arising from a mismatch of its input part device.
Japanese Unexamined Patent Application Publication No. 2008-219404 discloses an amplifier circuit including a chopper amplifier and an averaging circuit. The averaging circuit samples an output voltage of the chopper amplifier at multiple sampling times, and generates an average voltage of the output voltages at the sampling times.
Japanese Unexamined Patent Application Publication No. 2011-135225 discloses an adder circuit that adds an output voltage of a chopper amplifier and a hold voltage of a first sample and hold circuit between a first timing at which positive/negative of the offset voltage that is superimposed on the output voltage of the chopper amplifier and a second timing at which the first sample and hold circuit performs sampling and holding.
U.S. Pat. No. 7,292,095 discloses an amplifier circuit including a chopper amplifier and a switched capacitor. The amplifier circuit removes an offset voltage whose positive/negative polarities invert at a predetermined period by chopping using a switched capacitor technology.